The process of verification is getting complex with every passing year; this is due to the fact that complexity of chips is increasing. With such an increasing design complexity, verification tends to consume up to 60-80% project resources and often represents a bottleneck. Having all this in mind, We has developed number of Verification IP’s, which has been created by verification engineers with decades of experience in verifying complex chips.

The Verification IP (VIP) for IEEE 1149.1 (JTAG) provides an efficient and simple way to verify and monitor the JTAG controller and collect data on bus. Our VIP for JTAG Verification IP is fully compliant with JTAG Standard of IEEE 1149.1/1149.6:

• Supports all types of Jtag operations and JTAG Standard of IEEE 1149.1/1149.6 registers.
• Supports all the JTAG connection modes.
• Operates as a Jtag BFM to drive stimulus, protocol checker, Monitor and data collector.